1. Field of the Invention
An aspect of this disclosure relates to a communication circuit and a method of adjusting a sampling clock signal.
2. Description of the Related Art
There are communication circuits such as a universal asynchronous receiver transmitter (UART) that convert an asynchronous serial signal into a parallel signal and vice versa.
FIG. 5 is a block diagram illustrating a configuration of a related-art communication circuit. In FIG. 5, it is assumed that communication data represented by FIG. 6(A) are input to a terminal 1 and then supplied to a received data sampling circuit 2. The received data sampling circuit 2 detects a start bit in the communication data, generates a sampling clock signal represented by FIG. 6(B), and samples the communication data at timings when the sampling clock signal is high to obtain received data represented by FIG. 6(C). The received data are supplied to a received data storing register 3 and stored in the received data storing register 3 under the control of a communication control circuit 4.
Meanwhile, Japanese Laid-Open Patent Publication No. 11-341089, for example, discloses a technology where three sets of data are captured for each symbol period and the code of the symbol is determined based on the captured data according to a majority rule.
With related-art communication circuits and technologies, however, the sampling clock timing is fixed. Therefore, if the timing of the sampling clock signal becomes out of sync with the timing of received data due to, for example, an error in detection timing of a start bit, it may become difficult to correctly sample the received data.